1. Field of the Invention
The present invention relates to a phase-locked loop (hereinafter referred to as the "PLL") circuit used in a receiver to reproduce clock signals synchronized with a transmitter in a communications system, in particular, to a PLL circuit for reproducing clocks from time data sent at random temporal intervals.
2. Description of the Related Art
As a typical means for reproducing clocks synchronized with a transmitter in a receiver in a communications system, a PLL method is used which reproduces clocks by demodulating, in the receiver, temporal data modulated and superposed on sent signals in the transmitter. The PLL method is, for example, described in document ITU-T (recommendation H.220.0).
Particularly, when digital signals are used to transmit data between a transmitter and a receiver, a digital signal processing type PLL (hereinafter referred to as the "DPLL") method is applied which converts analog phase data into the corresponding digital data, then performs digital signal processing for clock reproduction. The DPLL method is, for example, described in a document, "Response of an All Digital Phase-locked Loop" (Joseph Garodnick, et al, IEEE TRANS. COMM. Vol. COM-22, No. 6, June 1974, pp751-764).
The above phase-locked loop methods based on prior art including DPPL are accompanied by the problem that they cannot control phase fluctuation (jitters) that occurs in the vicinity of a sampling frequency. This means that an asynchronous communications network cannot be used as a communications network for connecting a transmitter and a receiver. For example, as shown in FIG. 9 where a transmitter and a receiver are connected via an ATM (async transfer mode) communications network 94, time data is read in the transmitter at random intervals from a timer counter 91 that counts time according to clocks with frequency fs (Hz) from a send reference clock source (OSC) 92, and sent to the ATM communications network 94 as time data 93. The time data 93 is read from the timer counter 91 at certain random intervals within Ts seconds, and its value (height) indicates elapsed time T from the previous reading.
The receiver receives time data 93 as received time data 95 via the ATM communications network 94. And clocks are reproduced by a PLL circuit 96. The time when received time data 95 arrives is varied by cell delay variation (hereinafter referred to as "CDV") in the ATM communications network 94.
Now that time data is expressed as 2 .pi.fs.multidot.nT, CDV in the ATM communications network 94 appears as phase fluctuation (jitters) 97. The past DPLL circuit based on prior art cannot control such phase fluctuation and, thus, causes signal quality deterioration. An async communications network cannot, therefore, be used as a communications network for connecting a transmitter and a receiver.
It is well known that a second-order PLL circuit has been developed which can implement control over same P--P value jitters. Also, a third-order PLL circuit that can reduce system pull-in time very much has been designed successfully. But, the past third-order PLL circuit that uses a dual integrator as the filter suffers the problem that it is not stable against high jitters.